Chittagong University of Engineering & Technology Entrance Exam Set

The question probes the understanding of fundamental principles of structural integrity and material science as applied in civil engineering, a core discipline at Chittagong University of Engineering & Technology. The scenario involves a proposed pedestrian bridge designed to span a river near Chittagong, requiring consideration of environmental factors and load-bearing capacities. The critical aspect is identifying the most suitable material for the primary load-bearing elements of the bridge, considering both strength and durability in a coastal environment. Steel alloys, particularly high-strength, corrosion-resistant variants, offer a superior combination of tensile strength, stiffness, and resistance to the saline atmosphere and potential moisture ingress common in coastal regions like Chittagong. Reinforced concrete, while robust, can be susceptible to chloride-induced corrosion in its steel reinforcement in such environments if not meticulously designed and maintained. Advanced composite materials, such as carbon fiber reinforced polymers (CFRP), offer excellent strength-to-weight ratios and corrosion resistance but are often prohibitively expensive for large-scale infrastructure projects like a pedestrian bridge, especially in the initial design phase where cost-effectiveness is a major consideration. Timber, while aesthetically pleasing and sustainable, generally lacks the long-term durability and high load-bearing capacity required for a bridge of this nature, particularly when exposed to constant humidity and potential marine borers. Therefore, high-strength steel alloys are the most appropriate choice for the primary structural components of this pedestrian bridge, balancing performance, longevity, and economic feasibility within the context of Chittagong’s environmental conditions.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the behavior of combinational circuits under varying input conditions and the implications for signal integrity and predictability. The scenario describes a situation where a combinational circuit, designed to produce a specific output based on its inputs, exhibits an unexpected output when one of its inputs transitions from a stable state to an indeterminate state (often represented as ‘X’ or ‘high-impedance’). In digital systems, combinational circuits are designed such that the output is solely a function of the current inputs. However, real-world implementations can deviate from ideal behavior due to factors like propagation delays, glitches, and the presence of floating inputs. A floating input, where a signal line is not actively driven to a logic high or low, can lead to unpredictable voltage levels within the circuit. This indeterminate state can propagate through the logic gates, causing the output to fluctuate erratically or settle to an unintended logic level. The core concept being tested is the robustness of a combinational circuit’s design against such non-ideal input conditions. A well-designed circuit should maintain a predictable output even when one input is momentarily indeterminate, or at least exhibit a defined behavior that can be managed. The problem implies that the circuit’s output is not stable or predictable when an input is in an indeterminate state. This suggests a lack of proper input handling or a design that is overly sensitive to noise or undefined signal levels. The most appropriate response identifies the fundamental characteristic of combinational logic that is being violated or challenged by the scenario. The output of a combinational circuit should always be a direct and predictable function of its current inputs. When an input is indeterminate, the output’s predictability is compromised. Therefore, the statement that best describes this situation is that the circuit’s output is no longer solely dependent on the defined logic states of its inputs, but is now influenced by the indeterminate state. This highlights a critical aspect of digital design: ensuring that circuits behave predictably even under less-than-ideal conditions, which is crucial for reliable system operation. The scenario points to a failure in achieving this predictability, making the output dependent on more than just the intended logic levels.

The scenario describes a digital communication system transmitting a signal through a noisy channel. The core concept being tested is the relationship between signal-to-noise ratio (SNR), bandwidth, and the maximum achievable data rate, as defined by Shannon’s Channel Capacity Theorem. The theorem states that the maximum rate at which information can be transmitted over a communication channel is given by \(C = B \log_2(1 + \frac{S}{N})\), where \(C\) is the channel capacity in bits per second, \(B\) is the bandwidth of the channel in Hertz, and \(\frac{S}{N}\) is the SNR. In this problem, we are given the bandwidth \(B = 4 \text{ kHz}\) and the SNR \(\frac{S}{N} = 1000\). We need to calculate the channel capacity \(C\). Using the Shannon-Shannon theorem formula: \(C = B \log_2(1 + \frac{S}{N})\) \(C = 4000 \text{ Hz} \times \log_2(1 + 1000)\) \(C = 4000 \text{ Hz} \times \log_2(1001)\) To calculate \(\log_2(1001)\), we can use the change of base formula: \(\log_2(x) = \frac{\log_{10}(x)}{\log_{10}(2)}\) or \(\log_2(x) = \frac{\ln(x)}{\ln(2)}\). \(\log_2(1001) \approx \frac{\log_{10}(1001)}{\log_{10}(2)} \approx \frac{3.00043}{0.30103} \approx 9.967\) Alternatively, since \(2^{10} = 1024\), \(\log_2(1001)\) will be slightly less than 10. A more precise calculation yields approximately 9.967. Now, substitute this value back into the capacity formula: \(C \approx 4000 \text{ Hz} \times 9.967 \text{ bits/symbol}\) \(C \approx 39868 \text{ bits/second}\) Rounding to a more practical number, the maximum achievable data rate is approximately 39.87 kbps. This calculation demonstrates the fundamental limit on data transmission for a given channel, a concept crucial for understanding the design and limitations of communication systems studied at Chittagong University of Engineering & Technology. The theorem highlights how increasing bandwidth or SNR directly impacts the potential data throughput, guiding engineers in optimizing system performance within physical constraints. Understanding this principle is vital for students pursuing degrees in Electrical and Electronic Engineering or Computer Science and Engineering at CUET, as it underpins the efficiency of modern digital networks and wireless communication.

The question assesses understanding of fundamental principles in material science and engineering, particularly concerning the behavior of materials under stress and the factors influencing their mechanical properties. The scenario involves a hypothetical material developed for advanced structural applications at Chittagong University of Engineering & Technology (CUET). The core concept tested is the relationship between microstructure, processing, and macroscopic mechanical performance, specifically focusing on creep resistance. Creep is the tendency of a solid material to move slowly or deform permanently under the influence of persistent mechanical stresses. It is a time-dependent strain that occurs at elevated temperatures. Factors that enhance creep resistance typically involve microstructural features that impede dislocation movement and grain boundary sliding. These include: 1. **Grain Size:** Smaller grain sizes generally improve creep resistance at lower temperatures due to increased grain boundary area, which can hinder dislocation motion. However, at very high temperatures, larger grains can be beneficial as they reduce the total grain boundary area, which is a common site for creep deformation via grain boundary sliding. The question implies an advanced material, suggesting a need for high-temperature performance. 2. **Precipitation Hardening:** The presence of finely dispersed, stable precipitate particles within the material matrix acts as obstacles to dislocation movement, significantly increasing yield strength and creep resistance. These precipitates effectively “pin” dislocations, preventing them from gliding. 3. **Solid Solution Strengthening:** Alloying elements dissolved in the matrix can distort the crystal lattice, creating stress fields that impede dislocation motion. 4. **Work Hardening (Strain Hardening):** Introducing dislocations through plastic deformation can increase resistance to further deformation. However, at elevated temperatures, recovery processes can reduce the effectiveness of work hardening. 5. **Phase Stability:** The presence of stable, high-melting-point phases or intermetallic compounds can significantly improve creep resistance by providing structural integrity at elevated temperatures. Considering the need for superior creep resistance in advanced structural applications, the most effective strategy would involve a combination of microstructural elements that hinder dislocation motion and grain boundary sliding at high temperatures. Precipitation hardening with stable, finely dispersed particles is a well-established and highly effective method for enhancing creep resistance. These precipitates act as strong barriers to dislocation climb and glide, which are the primary mechanisms of creep deformation at elevated temperatures. While grain refinement can be beneficial, its effectiveness can diminish at very high temperatures where grain boundary sliding becomes dominant. Solid solution strengthening and work hardening are also important but often less impactful for extreme high-temperature creep resistance compared to well-designed precipitation strengthening. Therefore, the development of a material with a microstructure characterized by stable, finely dispersed precipitates within a ductile matrix would be the most promising approach for achieving exceptional creep resistance for demanding applications at CUET.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the minimization of Boolean expressions and the implications of Karnaugh maps (K-maps) in simplifying logic circuits. The scenario describes a digital circuit designed to control a water purification system at Chittagong University of Engineering & Technology, where a specific output \(Y\) is dependent on three input variables: \(A\) (pump status), \(B\) (water level sensor), and \(C\) (purity sensor). The truth table provided dictates the output \(Y\) for each combination of inputs. To determine the most efficient implementation, we need to derive the minimal Sum of Products (SOP) or Product of Sums (POS) form. Let’s analyze the truth table: | A | B | C | Y | |—|—|—|—| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | From the truth table, the minterms for which \(Y=1\) are: \(m_1, m_3, m_4, m_5, m_7\). In SOP form, this is \(Y = \bar{A}\bar{B}C + \bar{A}BC + A\bar{B}\bar{C} + A\bar{B}C + ABC\). Now, let’s construct a Karnaugh map for three variables: “` BC 00 01 11 10 A 0 | 0 1 1 0 | 1 | 1 1 1 0 | “` Grouping the 1s: 1. Group of four: \(m_1, m_3, m_5, m_7\) can be grouped together. This group covers the cells where \(C=1\) and \(A=1\) or \(A=0\), and \(B=0\) or \(B=1\). However, this is not the most optimal grouping. 2. Grouping the 1s for minimal SOP: – Group 1: \(m_1\) and \(m_3\) (\(\bar{A}C\)) – Group 2: \(m_4\) and \(m_5\) (\(A\bar{B}\)) – Group 3: \(m_5\) and \(m_7\) (\(AC\)) – This is incorrect as \(m_5\) is \(A\bar{B}C\) and \(m_7\) is \(ABC\). The common term is \(AC\). – Group 4: \(m_1\) and \(m_5\) – not adjacent. – Group 5: \(m_3\) and \(m_7\) (\(AC\)) – Group 6: \(m_4\) and \(m_7\) – not adjacent. Let’s re-examine the K-map and optimal grouping: The 1s are at positions (001), (011), (100), (101), (111). “` BC 00 01 11 10 A 0 | 0 1 1 0 | (m1, m3) 1 | 1 1 1 0 | (m4, m5, m7) “` Optimal groupings: 1. A group of four: \(m_1, m_3, m_5, m_7\). This covers cells (001), (011), (101), (111). The common terms are \(C\) and \(A\) is changing, \(B\) is changing. This group simplifies to \(C\). 2. A group of two: \(m_4, m_5\). This covers cells (100), (101). The common terms are \(A\) and \(\bar{B}\). This group simplifies to \(A\bar{B}\). So, the minimal SOP expression is \(Y = C + A\bar{B}\). Let’s verify this: – If \(C=1\), \(Y=1\) regardless of \(A\) and \(B\). This matches \(m_1, m_3, m_5, m_7\). – If \(C=0\), then \(Y = A\bar{B}\). – If \(A=0, B=0, C=0\), \(Y = 0\). Matches \(m_0\). – If \(A=0, B=1, C=0\), \(Y = 0\). Matches \(m_2\). – If \(A=1, B=0, C=0\), \(Y = 1\). Matches \(m_4\). – If \(A=1, B=1, C=0\), \(Y = 0\). Matches \(m_6\). This minimal SOP expression \(Y = C + A\bar{B}\) requires one OR gate and one AND gate with an inverter for \(B\). This is a highly efficient implementation. Now let’s consider the POS form. We need to group the zeros. The zeros are at \(m_0, m_2, m_6\). The POS expression is \(Y = (\bar{A} + \bar{B} + \bar{C})(\bar{A} + B + \bar{C})(A + B + \bar{C})\). Using a K-map for POS: “` BC 00 01 11 10 A 0 | 0 1 1 0 | (m0, m2) 1 | 1 1 1 0 | (m6) “` The zeros are at (000), (010), (110). Grouping the zeros: 1. Group of three: \(m_0, m_2, m_6\). This is not a valid grouping as they are not adjacent in a way that forms a rectangle or covers the entire map. 2. Grouping the zeros: – Group 1: \(m_0\) and \(m_2\). Common terms are \(\bar{A}\) and \(\bar{C}\). This gives \((\bar{A} + \bar{C})\). – Group 2: \(m_2\) and \(m_6\). Common terms are \(B\) and \(\bar{C}\). This gives \((B + \bar{C})\). – Group 3: \(m_0\) and \(m_6\) are not adjacent. Let’s re-examine the POS grouping. We need to cover all the zeros with the minimum number of prime implicants. Zeros are at: 000, 010, 110. The K-map for zeros: “` BC 00 01 11 10 A 0 | X . . X | (m0, m2) 1 | . . . X | (m6) “` Here, ‘.’ represents a ‘1’ and ‘X’ represents a ‘0’. “` BC 00 01 11 10 A 0 | 0 1 1 0 | 1 | 1 1 1 0 | “` Zeros are at (000), (010), (110). 1. Group of two zeros: \(m_0\) and \(m_2\). This is \(\bar{A}\bar{C}\). The POS term is \((\bar{A} + \bar{C})\). 2. Group of two zeros: \(m_2\) and \(m_6\). This is \(B\bar{C}\). The POS term is \((B + \bar{C})\). The minimal POS expression is \(Y = (\bar{A} + \bar{C})(B + \bar{C})\). Let’s expand this: \(Y = B\bar{A} + \bar{A}\bar{C} + B\bar{C} + \bar{C}\bar{C} = B\bar{A} + \bar{A}\bar{C} + B\bar{C} + \bar{C}\). Using absorption law \(X + X\bar{Y} = X\), we have \(\bar{C} + B\bar{C} = \bar{C}\) and \(\bar{C} + \bar{A}\bar{C} = \bar{C}\). So, \(Y = B\bar{A} + \bar{C}\). This is the same as \(Y = \bar{C} + A\bar{B}\) by De Morgan’s laws. \( \overline{(\bar{C} + A\bar{B})} = \overline{\bar{C}} \cdot \overline{(A\bar{B})} = C \cdot (\bar{A} + B) = C\bar{A} + CB \). This is not the same. Let’s re-evaluate the POS. The minimal POS expression is derived by grouping the zeros. Zeros are at \(m_0, m_2, m_6\). K-map for zeros: “` BC 00 01 11 10 A 0 | 0 . . 0 | 1 | . . . 0 | “` Groupings for zeros: 1. Group of two: \(m_0\) and \(m_2\). This covers the cells where \(A=0\) and \(C=0\). The implicant is \(\bar{A}\bar{C}\). The corresponding POS term is \((\bar{A} + \bar{C})\). 2. Group of two: \(m_2\) and \(m_6\). This covers the cells where \(B=1\) and \(C=0\). The implicant is \(B\bar{C}\). The corresponding POS term is \((B + \bar{C})\). The minimal POS expression is \(Y = (\bar{A} + \bar{C})(B + \bar{C})\). Let’s check the number of gates for this POS expression. \(Y = (\bar{A} + \bar{C})(B + \bar{C})\) requires: – Two NOT gates (for \(\bar{A}\) and \(\bar{C}\)). – Two OR gates (for \((\bar{A} + \bar{C})\) and \((B + \bar{C})\)). – One AND gate (to combine the two OR gate outputs). Total gates: 2 NOT + 2 OR + 1 AND = 5 gates. Now let’s consider the minimal SOP expression: \(Y = C + A\bar{B}\). This requires: – One NOT gate (for \(\bar{B}\)). – One AND gate (for \(A\bar{B}\)). – One OR gate (to combine \(C\) and \(A\bar{B}\)). Total gates: 1 NOT + 1 AND + 1 OR = 3 gates. Comparing the two minimal forms, the SOP form \(Y = C + A\bar{B}\) is more efficient in terms of the number of gates required for implementation. This is a crucial consideration in digital circuit design for minimizing cost, power consumption, and propagation delay, aligning with the engineering principles emphasized at Chittagong University of Engineering & Technology. The question asks for the most efficient implementation in terms of gate count. The minimal SOP form \(Y = C + A\bar{B}\) is indeed the most efficient implementation. Final Answer is \(C + A\bar{B}\).

The question probes the understanding of fundamental principles of digital logic design, specifically concerning the behavior of combinational logic circuits under varying input conditions and the implications for signal integrity and predictable operation. The scenario describes a situation where a specific logic gate’s output is intended to transition from a high state to a low state. However, due to the inherent propagation delays within the gate and the subsequent logic, the transition is not instantaneous. The critical aspect is to identify which of the provided statements accurately describes the state of the output signal *during* this transition period, considering that the output is not yet definitively ‘0’ but is in the process of changing. In digital electronics, propagation delay is the time it takes for a logic gate to respond to a change in its input. During this delay, the output of the gate is in an indeterminate or transitional state, neither a stable ‘0’ nor a stable ‘1’. This is often referred to as a “metastable” state, although in simpler terms for this context, it’s a period of transition. If this transitional output is fed into another logic gate, it can lead to unpredictable behavior, such as glitches or incorrect logic operations, especially if the setup and hold times of the subsequent gate are violated. The question asks about the state of the output signal *after* the input has changed but *before* the output has fully settled to its new stable state. This period is characterized by the output voltage moving from its initial high voltage level towards its final low voltage level. During this time, the output voltage is typically within the undefined region of the logic family’s voltage transfer characteristic, meaning it is neither a valid logic high nor a valid logic low. Therefore, the output signal is in a state of flux, actively transitioning. The correct answer must reflect this transitional nature. It is not a stable ‘0’, nor is it a stable ‘1’. It is also not necessarily a glitch, as a glitch implies a momentary incorrect output that then corrects itself; this is a continuous transition. The most accurate description is that the output is in a state of transition, moving from high to low.

The question assesses understanding of fundamental principles in structural mechanics, specifically concerning the behavior of beams under load and the concept of neutral axis. For a uniformly distributed load (UDL) on a simply supported beam, the bending moment is maximum at the center of the span. The neutral axis of a beam is the line along which the material experiences neither tension nor compression. In a homogeneous and symmetric beam cross-section, the neutral axis passes through the centroid of the cross-section. The bending stress distribution across the depth of the beam is linear, with zero stress at the neutral axis and maximum stress at the extreme fibers (top and bottom). For a simply supported beam with a UDL, the bending moment diagram is parabolic, with the maximum bending moment occurring at the mid-span. This maximum bending moment induces the maximum bending stress. The question asks about the location of zero bending stress. The bending stress is directly proportional to the bending moment and inversely proportional to the section modulus. However, the bending stress is also zero at the neutral axis regardless of the magnitude of the bending moment. Therefore, the location where bending stress is zero is always the neutral axis. The neutral axis is determined by the geometry of the cross-section and is independent of the applied load. For a standard rectangular or I-beam cross-section, the neutral axis is located at the geometric center of the cross-section. This fundamental concept is crucial for understanding beam design and analysis in civil and mechanical engineering disciplines at Chittagong University of Engineering & Technology.

The question probes the understanding of fundamental principles of electrical circuits and their behavior under specific conditions, relevant to the foundational courses at Chittagong University of Engineering & Technology. The scenario describes a simple series RC circuit. The core concept being tested is the transient response of an RC circuit when subjected to a DC voltage source after being initially discharged. When a DC voltage \(V_s\) is applied to a series RC circuit with an initially discharged capacitor, the voltage across the capacitor \(V_c(t)\) and the current \(I(t)\) through the circuit follow exponential charging behavior. The governing differential equation for the capacitor voltage is \(V_s = I(t)R + V_c(t)\), where \(I(t) = C \frac{dV_c(t)}{dt}\). Substituting \(I(t)\) gives \(V_s = RC \frac{dV_c(t)}{dt} + V_c(t)\). The solution to this first-order linear differential equation, with the initial condition \(V_c(0) = 0\), is \(V_c(t) = V_s(1 – e^{-t/RC})\). The time constant for this circuit is denoted by \(\tau = RC\). The question asks about the state of the capacitor voltage after a time equal to the time constant (\(t = \tau\)). Substituting \(t = \tau = RC\) into the equation for \(V_c(t)\): \(V_c(\tau) = V_s(1 – e^{-\tau/RC})\) \(V_c(\tau) = V_s(1 – e^{-RC/RC})\) \(V_c(\tau) = V_s(1 – e^{-1})\) The value of \(e^{-1}\) is approximately \(0.36788\). Therefore, \(V_c(\tau) = V_s(1 – 0.36788)\) \(V_c(\tau) = V_s(0.63212)\) This means that after one time constant, the capacitor voltage reaches approximately 63.2% of the source voltage. This is a fundamental characteristic of RC circuits and is crucial for understanding charging and discharging phenomena, which are foundational concepts in electronics and electrical engineering programs at Chittagong University of Engineering & Technology. Understanding time constants is vital for designing filters, timing circuits, and analyzing the dynamic behavior of electronic systems. The ability to predict the capacitor’s charge level at specific times is essential for many practical applications encountered in the curriculum.

The question revolves around the fundamental principles of electrical circuit analysis, specifically focusing on the behavior of capacitors and inductors in a series RLC circuit when subjected to a sinusoidal voltage source. The core concept being tested is the impedance of these components and how they collectively influence the circuit’s response, particularly the phase relationship between voltage and current. For a series RLC circuit driven by a sinusoidal voltage \(V(t) = V_m \sin(\omega t)\), the total impedance \(Z\) is given by \(Z = R + j(X_L – X_C)\), where \(R\) is the resistance, \(X_L = \omega L\) is the inductive reactance, and \(X_C = \frac{1}{\omega C}\) is the capacitive reactance. The magnitude of the impedance is \(|Z| = \sqrt{R^2 + (X_L – X_C)^2}\). The phase angle \(\phi\) between the voltage and current is given by \(\tan(\phi) = \frac{X_L – X_C}{R}\). In this specific scenario, we are given that the current leads the voltage by \(30^\circ\). In a series RLC circuit, current leads voltage when the circuit is predominantly capacitive, meaning the capacitive reactance is greater than the inductive reactance (\(X_C > X_L\)). A leading phase angle signifies that the current reaches its peak before the voltage does. The angle of lead is negative in the standard convention where the voltage is the reference. Therefore, a \(30^\circ\) lead of current means the phase angle \(\phi\) is \(-30^\circ\). Using the phase angle formula: \[ \tan(\phi) = \frac{X_L – X_C}{R} \] Substituting \(\phi = -30^\circ\): \[ \tan(-30^\circ) = \frac{X_L – X_C}{R} \] We know that \(\tan(-30^\circ) = -\frac{1}{\sqrt{3}}\). So, \[ -\frac{1}{\sqrt{3}} = \frac{X_L – X_C}{R} \] Rearranging this equation to find the relationship between the reactances and resistance: \[ R = -\sqrt{3}(X_L – X_C) \] \[ R = \sqrt{3}(X_C – X_L) \] This equation directly shows that \(X_C – X_L = \frac{R}{\sqrt{3}}\). This relationship is crucial for understanding the circuit’s behavior. The fact that the current leads the voltage by \(30^\circ\) indicates that the capacitive effect dominates the inductive effect, a characteristic that would be a key consideration for students at Chittagong University of Engineering & Technology when analyzing power factor correction or filter design. Understanding this phase relationship is fundamental to grasping how energy is stored and released in the reactive components, influencing the overall power delivery and efficiency of AC circuits, which are central to many electrical engineering disciplines at CUET.

The question probes the understanding of fundamental principles in digital logic design, specifically focusing on the behavior of combinational logic circuits when inputs are not explicitly defined. In digital systems, an input that is neither a definite logic ‘0’ nor a logic ‘1’ is represented as a ‘high-impedance’ state or ‘X’ (unknown). When such an ‘X’ input is fed into a combinational logic gate, the output’s state depends on the gate’s logic function and the nature of the ‘X’. Consider a simple AND gate. If one input is ‘0’ and the other is ‘X’, the output will always be ‘0’, regardless of the ‘X’ value (since \(0 \land 0 = 0\) and \(0 \land 1 = 0\)). However, if one input is ‘1’ and the other is ‘X’, the output will be ‘X’ because the output could be either ‘0’ (if ‘X’ is ‘0’) or ‘1’ (if ‘X’ is ‘1’). This uncertainty propagates through the circuit. For a NAND gate, the output is the inverse of the AND gate. So, if the AND gate output is ‘0’, the NAND gate output is ‘1’. If the AND gate output is ‘X’, the NAND gate output is also ‘X’ (since the inverse of ‘X’ is still ‘X’). In the given scenario, a combinational circuit at Chittagong University of Engineering & Technology is designed with a specific input configuration. The circuit’s behavior is being analyzed under a condition where a specific input line is left floating, effectively creating a high-impedance state. This floating input is then connected to a logic gate. The question asks about the predictable output state of the circuit under this condition. If a floating input (represented as ‘X’) is connected to an input of a NAND gate, and the other input of the NAND gate is a logic ‘1’, the output of the NAND gate will be ‘X’. This is because the NAND gate’s output is the inverse of the AND gate’s output. For the AND gate, \(1 \land X\) results in \(X\). The inverse of \(X\) is still \(X\). Therefore, the output of the NAND gate will be ‘X’. This ‘X’ state signifies that the output is unpredictable and could be either ‘0’ or ‘1’ depending on the actual voltage level that the floating input eventually settles to, or how it is interpreted by subsequent logic. This unpredictability is a critical consideration in robust digital system design, especially in environments like those studied at Chittagong University of Engineering & Technology, where reliable operation is paramount. The presence of ‘X’ states can lead to indeterminate behavior and potential functional failures if not handled properly through design techniques like pull-up or pull-down resistors.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the behavior of combinational logic circuits under specific input conditions. The scenario describes a circuit with inputs A, B, and C, and an output Y. The truth table provided defines the output for all possible input combinations. The task is to identify the Boolean expression that accurately represents this truth table. Let’s analyze the truth table: | A | B | C | Y | |—|—|—|—| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | We look for the rows where Y is 1. These are: 1. A=0, B=0, C=1: This corresponds to the minterm \(\bar{A}\bar{B}C\). 2. A=0, B=1, C=0: This corresponds to the minterm \(\bar{A}B\bar{C}\). 3. A=0, B=1, C=1: This corresponds to the minterm \(\bar{A}BC\). 4. A=1, B=1, C=0: This corresponds to the minterm \(ABC\bar{C}\). 5. A=1, B=1, C=1: This corresponds to the minterm \(ABC\). The Sum of Products (SOP) expression is the OR of these minterms: \(Y = \bar{A}\bar{B}C + \bar{A}B\bar{C} + \bar{A}BC + ABC\bar{C} + ABC\) Now, let’s simplify this expression using Boolean algebra. Notice that \(\bar{A}B\bar{C} + \bar{A}BC = \bar{A}B(\bar{C} + C) = \bar{A}B(1) = \bar{A}B\). So, the expression becomes: \(Y = \bar{A}\bar{B}C + \bar{A}B + ABC\bar{C} + ABC\) Also, \(ABC\bar{C} = ABC(0) = 0\). This term is redundant. So, \(Y = \bar{A}\bar{B}C + \bar{A}B + ABC\) Let’s re-examine the truth table and look for simplifications directly. Rows where Y=1: – \(001 \rightarrow \bar{A}\bar{B}C\) – \(010 \rightarrow \bar{A}B\bar{C}\) – \(011 \rightarrow \bar{A}BC\) – \(110 \rightarrow AB\bar{C}\) – \(111 \rightarrow ABC\) Combining \(\bar{A}B\bar{C} + \bar{A}BC = \bar{A}B(\bar{C}+C) = \bar{A}B\). Combining \(AB\bar{C} + ABC = AB(\bar{C}+C) = AB\). So, \(Y = \bar{A}\bar{B}C + \bar{A}B + AB\) Now, combine \(\bar{A}B + AB = B(\bar{A}+A) = B(1) = B\). So, \(Y = \bar{A}\bar{B}C + B\) Let’s check if this simplified expression matches the truth table. If B=1, Y=1, regardless of A and C. This covers rows 3, 4, 7, 8. – Row 3: A=0, B=1, C=0. Y=1. Matches. – Row 4: A=0, B=1, C=1. Y=1. Matches. – Row 7: A=1, B=1, C=0. Y=1. Matches. – Row 8: A=1, B=1, C=1. Y=1. Matches. If B=0, then Y depends on \(\bar{A}\bar{B}C\). Since B=0, \(\bar{B}=1\), so Y depends on \(\bar{A}C\). – Row 1: A=0, B=0, C=0. \(\bar{A}C = (1)(0) = 0\). Y=0. Matches. – Row 2: A=0, B=0, C=1. \(\bar{A}C = (1)(1) = 1\). Y=1. Matches. – Row 5: A=1, B=0, C=0. \(\bar{A}C = (0)(0) = 0\). Y=0. Matches. – Row 6: A=1, B=0, C=1. \(\bar{A}C = (0)(1) = 0\). Y=0. Matches. The simplified expression \(Y = \bar{A}\bar{B}C + B\) correctly represents the given truth table. This question is designed to test a candidate’s ability to translate a truth table into a Boolean expression and then simplify it using fundamental Boolean algebra laws. This is a core skill in digital logic design, a foundational subject for many engineering disciplines offered at Chittagong University of Engineering & Technology, such as Electrical and Electronic Engineering, Computer Science and Engineering, and Information Technology. The ability to simplify logic expressions is crucial for designing efficient and cost-effective digital circuits, minimizing the number of gates required, reducing power consumption, and improving performance. Understanding these concepts is vital for students who will be working with microprocessors, digital signal processing, and embedded systems, all areas of significant research and academic focus at CUET. The simplification process involves applying laws like the distributive law, associative law, commutative law, identity law, complement law, idempotence law, absorption law, and consensus theorem. Mastery of these techniques allows engineers to represent complex logic functions in their most compact form.

The question probes the understanding of fundamental principles in materials science and engineering, specifically focusing on the relationship between crystal structure, atomic bonding, and macroscopic properties relevant to materials used in advanced engineering applications, a core area of study at Chittagong University of Engineering & Technology. The scenario describes a hypothetical new alloy exhibiting unusual mechanical behavior under tensile stress, characterized by a sharp drop in stress after reaching a peak, followed by a period of constant stress before further deformation. This behavior is indicative of a specific failure or deformation mechanism. To determine the most likely underlying cause, we analyze the options in the context of common material behaviors: 1. **Brittle fracture:** This typically involves a sudden, catastrophic failure with little to no plastic deformation, characterized by a sharp peak stress and then a rapid drop to zero. The scenario describes a period of constant stress, ruling this out as the primary explanation. 2. **Ductile fracture with work hardening:** Ductile materials exhibit significant plastic deformation. Work hardening causes the stress required to continue deformation to increase after yielding. While ductile fracture involves plastic deformation, the described stress-strain curve (peak stress followed by constant stress) is not typical of simple work hardening, which would usually show a continuous increase in stress with strain until fracture. 3. **Phase transformation during deformation:** Some materials undergo solid-state phase transformations when subjected to stress or strain. If a new, weaker phase forms or an existing phase becomes less resistant to deformation under the applied stress, it could lead to a drop in the required stress to maintain deformation, followed by a plateau if the transformation saturates or a new equilibrium is reached. This behavior aligns with the observed stress-strain curve, where the initial peak represents the yield strength of the original phase, and the subsequent plateau indicates a lower stress is needed to continue deformation due to a stress-induced phase change. This concept is crucial for understanding the design of advanced alloys and their performance under extreme conditions, a focus at CUET. 4. **Elastic instability (Buckling):** Buckling is a phenomenon typically associated with compressive stress in slender structural elements, not tensile stress. It leads to a sudden loss of stiffness but is not directly related to the stress-strain behavior described under tension. Therefore, a stress-induced phase transformation is the most plausible explanation for the observed stress-strain behavior in the hypothetical alloy. This understanding is vital for materials engineers at CUET, as it informs material selection and design for applications requiring predictable mechanical responses under varying loads.

The question probes the understanding of the fundamental principles of electrical circuit analysis, specifically focusing on the behavior of capacitors in a DC circuit after a significant time has passed. In a DC circuit, a capacitor acts as an open circuit once it is fully charged. This means that no current flows through the capacitor branch. Consider a circuit with a voltage source \(V_{source}\), a resistor \(R\), and a capacitor \(C\) connected in series. When the switch is closed at \(t=0\), the capacitor begins to charge. The voltage across the capacitor, \(V_C(t)\), is given by \(V_C(t) = V_{source}(1 – e^{-t/RC})\), and the current through the circuit is \(I(t) = \frac{V_{source}}{R}e^{-t/RC}\). The time constant of the RC circuit is denoted by \(\tau = RC\). After a duration of \(5\tau\), the capacitor is considered to be fully charged. At this point, the exponential term \(e^{-t/RC}\) approaches zero. Therefore, as \(t \to \infty\), \(e^{-t/RC} \to 0\). The voltage across the capacitor becomes \(V_C(\infty) = V_{source}(1 – 0) = V_{source}\). The current in the circuit becomes \(I(\infty) = \frac{V_{source}}{R} \times 0 = 0\). This implies that the capacitor effectively blocks the flow of DC current, behaving as an open circuit. Consequently, the potential difference across the resistor, \(V_R\), which is given by \(V_R = I \times R\), will also be zero since the current is zero. The potential difference across the capacitor will be equal to the source voltage. The question asks about the state of the circuit after a “very long time” in a DC steady-state condition. This implies that the transient behavior has subsided, and the circuit has reached its steady state. In this steady state, the capacitor is fully charged to the source voltage, and no current flows through the circuit. Thus, the voltage drop across any resistor in series with the capacitor will be zero. This principle is fundamental to understanding the behavior of capacitive circuits in direct current applications, a core concept in electrical engineering studies at Chittagong University of Engineering & Technology. Understanding this steady-state behavior is crucial for designing and analyzing circuits involving energy storage elements.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the behavior of combinational logic circuits when inputs are subjected to asynchronous changes, a critical consideration in the design of reliable digital systems at institutions like Chittagong University of Engineering & Technology. When multiple inputs to a combinational circuit change simultaneously, the output may temporarily settle to an incorrect value before reaching its final, stable state. This transient, erroneous output is known as a *glitch* or *hazard*. The phenomenon arises because different signal paths within the circuit have varying propagation delays. Consequently, the logic gates do not all update their outputs at precisely the same instant. For a circuit to be considered hazard-free, its output must remain stable and correct throughout the transition period, regardless of the input changes. The primary method to eliminate static hazards (where the output should remain constant but might momentarily change) and dynamic hazards (where the output should change once but might change multiple times) involves incorporating redundant logic paths that ensure the output remains stable during input transitions. This redundancy effectively masks the temporary incorrect states caused by differing propagation delays. Therefore, the most effective strategy to mitigate these transient output behaviors in combinational logic, ensuring predictable operation crucial for advanced engineering studies, is the introduction of redundant logic.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the behavior of combinational logic circuits under varying input conditions and the implications for signal integrity and predictable operation. The scenario describes a situation where a critical signal, intended to be stable, exhibits erratic behavior. This points towards a potential issue with the design’s robustness against noise or timing variations. Consider a scenario where a combinational logic circuit designed for the Chittagong University of Engineering & Technology’s Electrical and Electronic Engineering department is intended to produce a stable output based on its inputs. However, during testing, the output signal fluctuates unpredictably, even when the input signals are held constant. This phenomenon is often a consequence of race conditions or hazards within the combinational logic. A hazard is a transient, undesirable output that occurs when a change in input signals causes the output to momentarily take an incorrect value before settling to the correct steady-state value. In combinational circuits, these can arise from differing propagation delays through different logic gate paths that converge at a common output. If not properly addressed, these hazards can lead to metastable states or incorrect operation in sequential circuits that use the output of the combinational logic. The most common types of hazards in combinational logic are static, dynamic, and essential hazards. Static hazards occur when the output should remain constant but momentarily changes. Dynamic hazards occur when the output changes multiple times when it should only change once. Essential hazards are a more complex type that can cause a circuit to fail to reach a stable state. In the context of the described erratic output, a static hazard is the most likely culprit, particularly a ‘1-0-1’ or ‘0-1-0’ transition when the output should remain at a constant logic level. These are often caused by the way the logic is implemented and can be mitigated through techniques like Karnaugh map simplification that includes redundant terms to cover all input transitions, or by using specific circuit design methodologies that inherently avoid hazards. The presence of such hazards is a critical consideration in digital system design, especially in high-speed applications or where reliable operation is paramount, aligning with the rigorous standards expected in engineering education at Chittagong University of Engineering & Technology. The ability to identify and mitigate these issues is a core competency for electrical and electronic engineers.

The question probes the understanding of the fundamental principles of structural integrity and material science as applied in civil engineering, a core discipline at Chittagong University of Engineering & Technology. The scenario involves a bridge designed to withstand specific environmental loads, including seismic activity, which is a significant consideration for the region. The core concept being tested is the relationship between material properties, structural design, and the ability to resist dynamic forces. Specifically, it focuses on how the inherent damping characteristics of a material influence its response to vibrations induced by seismic events. Materials with higher damping coefficients can dissipate vibrational energy more effectively, reducing the amplitude of oscillations and thus the stress experienced by the structure. This leads to a lower probability of failure or permanent deformation. For instance, certain advanced composite materials or specially engineered alloys often exhibit superior damping properties compared to traditional materials like plain concrete or mild steel. The question requires an understanding that while tensile strength and Young’s modulus are crucial for static load bearing, damping capacity is paramount for dynamic resilience, particularly against unpredictable forces like earthquakes. A higher damping ratio means that for a given input of vibrational energy, the material will return to its equilibrium state more quickly and with less residual oscillation, thereby protecting the overall structural integrity. This is a critical consideration in the design of infrastructure in seismically active zones, a relevant context for engineering education in Bangladesh.

The question probes the understanding of fundamental principles of electrical circuits, specifically concerning the behavior of capacitors and inductors in AC circuits and their impact on power factor. In an AC circuit, the power factor is defined as the cosine of the phase angle between the voltage and current. It represents the ratio of real power (dissipated as heat) to apparent power (total power supplied). A leading power factor indicates that the current leads the voltage, typically caused by capacitive loads. A lagging power factor indicates that the current lags the voltage, typically caused by inductive loads. Consider a scenario where a Chittagong University of Engineering & Technology (CUET) electrical engineering student is analyzing a circuit with a non-unity power factor. If the circuit exhibits a leading power factor, it implies that the net reactance in the circuit is capacitive. This means the capacitive reactance (\(X_C\)) is greater than the inductive reactance (\(X_L\)). The impedance of the circuit is given by \(Z = R + j(X_L – X_C)\), where \(R\) is the resistance. The phase angle \(\phi\) is given by \(\tan(\phi) = \frac{X_L – X_C}{R}\). For a leading power factor, \(\phi\) is negative, meaning \(X_L – X_C < 0\), or \(X_C > X_L\). The power factor is \(\cos(\phi)\). If a circuit has a leading power factor, it means that the capacitive component of the circuit is dominant. This leads to the current waveform preceding the voltage waveform. In practical terms, this often occurs in circuits with a significant capacitive load, such as those with large banks of capacitors or certain types of electronic equipment. The power factor correction techniques typically aim to bring the power factor closer to unity. For a leading power factor, this is usually achieved by adding inductive elements (like inductors) to counteract the excess capacitance. The question asks about the consequence of a leading power factor, which is directly related to the phase relationship between voltage and current. A leading power factor signifies that the current leads the voltage.

The question probes the understanding of the fundamental principles of data integrity and security in a modern computing context, specifically relevant to the rigorous academic and research environment at Chittagong University of Engineering & Technology. The scenario involves a distributed system where data consistency and authenticity are paramount. Consider a scenario where a research team at Chittagong University of Engineering & Technology is collaborating on a project involving sensitive experimental data. This data is stored across multiple nodes in a decentralized network. To ensure that the data remains unaltered and its origin is verifiable, a cryptographic hashing mechanism is employed. Each block of data is associated with a unique hash value, and crucially, each subsequent block also contains the hash of the preceding block. This creates a chain of dependencies. If an unauthorized party attempts to tamper with a single data point in an earlier block, the hash of that block will change. Consequently, the stored hash of that block in the next block will no longer match the recalculated hash, breaking the chain. This cascading effect makes any modification immediately detectable. The core concept being tested is the immutability and tamper-evidence provided by cryptographic hashing in a blockchain-like structure, which is a foundational element in many advanced computing fields taught at CUET, such as cybersecurity, distributed systems, and data science. The integrity of the data is maintained not by a single point of control, but by the inherent mathematical properties of the hashing algorithm and the linked structure of the data blocks. This distributed trust model is vital for ensuring the reliability of research findings and the security of digital assets within an academic institution. The question assesses the candidate’s ability to connect theoretical cryptographic principles to practical data security challenges in a distributed computing environment, a skill highly valued in CUET’s curriculum.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the minimization of Boolean expressions and the implications of using different logic gates. The scenario describes a situation where a designer at Chittagong University of Engineering & Technology (CUET) is tasked with implementing a specific logic function using only NAND gates. The core concept being tested is the universality of NAND gates, meaning any Boolean function can be implemented using only NAND gates. To solve this, one must recall or derive the basic NAND gate equivalences for NOT, AND, and OR gates. 1. **NOT Gate:** A NOT gate can be implemented by connecting both inputs of a NAND gate together. If the input is A, then \(A \cdot A = A\), and the output of the NAND gate is \(\overline{A \cdot A} = \overline{A}\). 2. **AND Gate:** An AND gate can be implemented by first creating an AND gate and then inverting its output. An AND gate is \(A \cdot B\). If we NAND A and B, we get \(\overline{A \cdot B}\). To get \(A \cdot B\), we need to invert this output. Inverting \(\overline{A \cdot B}\) using a NAND gate (as a NOT gate) gives \(\overline{\overline{A \cdot B}} = A \cdot B\). So, two NAND gates are needed for an AND gate. 3. **OR Gate:** An OR gate can be implemented using De Morgan’s theorem. \(A + B = \overline{\overline{A} \cdot \overline{B}}\). This expression shows that we can achieve an OR gate by inverting A, inverting B, NANDing the inverted inputs, and then inverting the result. Each inversion is a NAND gate acting as a NOT gate, and the middle operation is a NAND gate. Thus, three NAND gates are required for an OR gate. The question asks about the *minimum* number of NAND gates required to implement a general Boolean function. While specific functions might require fewer, the question implies a general capability. The universality of NAND gates means any complex logic circuit can be constructed from them. The most efficient way to construct basic gates (AND, OR, NOT) from NAND gates sets the baseline for implementing any function. The most “expensive” basic gate in terms of NAND gate count is the OR gate, requiring three NAND gates. Since any Boolean function can be expressed in terms of AND, OR, and NOT operations (e.g., Sum of Products or Product of Sums), and these can be built from NAND gates, the ability to construct an OR gate from three NAND gates is crucial. Therefore, the capability to implement any Boolean function using only NAND gates is fundamentally linked to the ability to construct all basic logic operations. The question is subtly asking about the inherent capability and the underlying principle of NAND gate universality, which is demonstrated by its ability to form other gates. The most complex basic gate construction from NANDs dictates the general principle. The question is designed to test the understanding of gate universality and the underlying principles of digital logic synthesis, a core topic in electrical and electronic engineering programs at CUET. It requires recalling or deducing the NAND gate equivalents for NOT, AND, and OR gates and understanding that the ability to form the most complex of these (OR) from NAND gates demonstrates the universal nature of NAND. The question avoids direct calculation but requires conceptual understanding of Boolean algebra and logic gate implementation.

The question probes the understanding of the fundamental principles governing the operation of a basic diode circuit, specifically focusing on the concept of forward bias and the associated voltage drop. In a silicon PN junction diode, the typical forward voltage drop, often referred to as the turn-on voltage or threshold voltage, is approximately \(0.7\) Volts. This voltage is required to overcome the potential barrier at the PN junction, allowing significant current to flow. Consider a scenario where a silicon diode is connected in series with a \(1.5\) kΩ resistor and a \(5\) V DC power supply, with the diode oriented for forward bias. To determine the voltage across the resistor, we first account for the diode’s forward voltage drop. The total voltage supplied by the source is \(5\) V. When the diode is forward-biased, it effectively acts as a voltage source of approximately \(0.7\) V in series with the resistor. Therefore, the voltage available to be dropped across the resistor is the total supply voltage minus the diode’s forward voltage drop. Voltage across resistor = Total Supply Voltage – Diode Forward Voltage Drop Voltage across resistor = \(5\) V – \(0.7\) V = \(4.3\) V This \(4.3\) V is the voltage that will be dropped across the \(1.5\) kΩ resistor. The current flowing through the circuit can then be calculated using Ohm’s Law (\(I = V/R\)), which would be \(4.3\) V / \(1500\) Ω = \(0.002867\) A or \(2.867\) mA. However, the question specifically asks for the voltage across the resistor. The understanding of this forward voltage drop is crucial in analog circuit design, power electronics, and digital logic circuits, all of which are foundational to various engineering disciplines offered at Chittagong University of Engineering & Technology. For instance, in power supply design, accurately predicting voltage drops across diodes is essential for ensuring stable output voltages and preventing component damage. In digital circuits, the switching behavior of diodes, dictated by their forward voltage characteristics, influences signal integrity and logic level definitions. The ability to apply this fundamental concept in a practical circuit context demonstrates a candidate’s grasp of basic semiconductor device behavior, a prerequisite for advanced studies in electronics and related fields at Chittagong University of Engineering & Technology.

The question probes the understanding of fundamental principles of digital logic design, specifically concerning the minimization of Boolean expressions and the implications of Karnaugh maps (K-maps) in circuit simplification. The scenario describes a logic circuit designed to control a water purification system at Chittagong University of Engineering & Technology, where a specific output \(F\) depends on three input variables: \(A\) (pump status), \(B\) (water level sensor), and \(C\) (purity sensor). The provided truth table outlines the desired output for all possible input combinations. To determine the most efficient implementation, we analyze the truth table and derive the minimal Sum-of-Products (SOP) or Product-of-Sums (POS) form. | A | B | C | F | |—|—|—|—| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | From the truth table, the minterms where \(F=1\) are: \(A’BC’\), \(A’BC\), \(AB’C\), and \(ABC\). In SOP form, \(F = A’BC’ + A’BC + AB’C + ABC\). We can simplify this expression using Boolean algebra or a Karnaugh map. Using a K-map for three variables: “` BC A 00 01 11 10 — — — — — 0 | 0 0 1 1 | 1 | 0 1 1 0 | “` Grouping the 1s: 1. Group of two: \(A’BC’\) and \(A’BC\) simplify to \(A’B\). 2. Group of two: \(AB’C\) and \(ABC\) simplify to \(AC\). Therefore, the minimal SOP expression is \(F = A’B + AC\). This minimal expression requires two AND gates and one OR gate, resulting in a total of three gates. Let’s consider other potential implementations: – The original SOP expression \(F = A’BC’ + A’BC + AB’C + ABC\) would require four 3-input AND gates and one 4-input OR gate, totaling five gates. – A POS simplification might yield a different gate count. To find the POS form, we look at the zeros: \(A’B’C’\), \(A’B’C\), \(AB C’\), \(AB’C’\). The maxterms are \(A+B+C\), \(A+B+C’\), \(A’+B+C’\), \(A’+B’+C’\). The POS expression is \(F = (A+B+C)(A+B+C’)(A’+B+C’)(A’+B’+C’)\). Simplifying this POS form would also lead to a minimal expression. However, the SOP form \(A’B + AC\) is generally considered the most straightforward minimal representation for this truth table and is a common target for simplification exercises. The question asks for the most efficient implementation in terms of gate count. The minimal SOP form \(A’B + AC\) uses the fewest gates among common simplification methods. The implementation requires one NOT gate (for \(A’\)), two AND gates (for \(A’B\) and \(AC\)), and one OR gate (to combine \(A’B\) and \(AC\)). This totals four gates. However, if we consider that the NOT gate for \(A’\) might be shared or implicitly available, the core logic requires two AND gates and one OR gate. The question implies implementing the logic function, and the minimal SOP form \(A’B + AC\) is the most efficient representation using standard logic gates. The number of gates required for this minimal SOP is 1 NOT gate, 2 AND gates, and 1 OR gate, totaling 4 gates. The minimal SOP expression \(F = A’B + AC\) represents the most efficient implementation in terms of gate count for this specific logic function. This simplification is crucial in digital design to reduce hardware complexity, power consumption, and propagation delay, all vital considerations for systems at institutions like Chittagong University of Engineering & Technology, where robust and efficient designs are paramount. The ability to derive and apply Boolean algebra or K-maps to minimize logic functions is a foundational skill for aspiring engineers.

The question probes the understanding of fundamental principles of electrical circuits and their behavior under specific conditions, particularly relevant to the foundational courses at Chittagong University of Engineering & Technology. The scenario involves a series RL circuit. The core concept being tested is the transient response of an RL circuit when subjected to a DC voltage source after a period of steady state. Initially, the circuit is in a steady state with the switch closed, meaning the inductor acts as a short circuit, and the current flowing through it is determined solely by the voltage source and the resistor. The current at steady state is \(I_{steady} = \frac{V}{R}\). In this case, \(V = 12V\) and \(R = 4\Omega\), so \(I_{steady} = \frac{12V}{4\Omega} = 3A\). When the switch is opened at \(t=0\), the DC voltage source is disconnected, and the inductor’s stored energy begins to dissipate through the resistor. The circuit now becomes a source-free RL circuit. The current in an RL circuit during this discharge phase is given by the formula: \(I(t) = I_0 e^{-\frac{t}{\tau}}\), where \(I_0\) is the initial current at \(t=0\) (which is the steady-state current before the switch opened), and \(\tau\) is the time constant of the circuit. The time constant for an RL circuit is given by \(\tau = \frac{L}{R}\). In this problem, \(L = 2H\) and \(R = 4\Omega\). Therefore, the time constant is \(\tau = \frac{2H}{4\Omega} = 0.5s\). The initial current \(I_0\) is the steady-state current before the switch was opened, which is \(3A\). The question asks for the current through the inductor \(0.5s\) after the switch is opened. Plugging these values into the discharge equation: \(I(0.5s) = 3A \times e^{-\frac{0.5s}{0.5s}}\) \(I(0.5s) = 3A \times e^{-1}\) \(I(0.5s) = 3A \times \frac{1}{e}\) The value of \(e\) is approximately \(2.71828\). \(I(0.5s) \approx 3A \times \frac{1}{2.71828}\) \(I(0.5s) \approx 1.1036A\) This calculation demonstrates the exponential decay of current in an RL circuit after the removal of the voltage source. The time constant \(\tau\) represents the time it takes for the current to decay to approximately \(36.8\%\) of its initial value. Since the time elapsed is exactly one time constant (\(0.5s\)), the current will have decayed to \(e^{-1}\) times its initial value. This concept is fundamental to understanding transient analysis in electrical engineering, a core subject at CUET, and is crucial for designing and analyzing circuits involving inductors and capacitors, which are prevalent in power systems, control systems, and electronics. Understanding this decay behavior is essential for predicting circuit performance and ensuring stability in various applications.

The question assesses understanding of fundamental principles in electrical engineering, specifically related to circuit analysis and the behavior of components under varying conditions, a core area for Chittagong University of Engineering & Technology (CUET) students. The scenario involves a simple series circuit with a resistor and an inductor, powered by a DC source. When the switch is closed, the inductor resists the change in current. The current in an RL circuit with a DC source follows the equation \(I(t) = \frac{V}{R}(1 – e^{-\frac{R}{L}t})\). At \(t=0\), the current is \(I(0) = \frac{V}{R}(1 – e^0) = \frac{V}{R}(1 – 1) = 0\). This means the inductor initially acts as an open circuit, blocking the flow of current. As time progresses, the current builds up exponentially. The question asks about the state of the circuit *immediately* after the switch is closed. At this precise moment (\(t \to 0^+\)), the rate of change of current is maximal, and the induced voltage across the inductor, given by \(V_L = -L \frac{dI}{dt}\), is equal in magnitude and opposite in direction to the source voltage, effectively opposing the entire source voltage. This means the voltage across the resistor, \(V_R = IR\), must be zero, implying the current \(I\) is zero. Therefore, the inductor behaves as an open circuit at the instant the switch is closed. This concept is crucial for understanding transient behavior in electrical systems, a key topic in CUET’s electrical engineering curriculum.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the minimization of Boolean expressions and the implications of using different logic gates. The scenario describes a digital circuit designed to control a water purification system at Chittagong University of Engineering & Technology, where a specific output \(Y\) is dependent on three input signals: \(A\) (pump status), \(B\) (water level sensor), and \(C\) (system error flag). The provided truth table defines the desired behavior of the system. The truth table is: | A | B | C | Y | |—|—|—|—| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | From the truth table, we can identify the minterms where \(Y=1\): Minterms are: \(A’BC\), \(AB C’\), \(ABC\). The Sum of Products (SOP) expression is \(Y = A’BC + ABC’ + ABC\). To simplify this expression, we can use Boolean algebra or a Karnaugh map. Using Boolean algebra: \(Y = A’BC + ABC’ + ABC\) Factor out \(BC\) from the first two terms: \(Y = BC(A’ + A) + ABC’\) Since \(A’ + A = 1\): \(Y = BC(1) + ABC’\) \(Y = BC + ABC’\) Factor out \(B\) from both terms: \(Y = B(C + AC’)\) Using the absorption law \(X + XY’ = X + Y\), where \(X=C\) and \(Y=A\): \(C + AC’ = C + A\) So, \(Y = B(C + A)\) Distributing \(B\): \(Y = BC + BA\) This simplified expression \(Y = BA + BC\) represents the minimal Sum of Products form. This expression can be implemented using AND gates and an OR gate. Specifically, two AND gates (one for \(BA\) and one for \(BC\)) and one OR gate to combine their outputs. This is a standard and efficient implementation. Let’s consider the other options: – \(Y = A’BC + AB\): This expression is derived by incorrectly simplifying \(A’BC + ABC’ + ABC\). For instance, if one were to group \(A’BC + ABC\) as \(BC(A’+A) = BC\), and then combine \(BC + ABC’\), it doesn’t directly lead to \(A’BC + AB\). If we consider \(A’BC + ABC’ + ABC = A’BC + ABC’ + ABC + ABC\) (adding redundant term ABC), then \(A’BC + ABC = BC(A’+A) = BC\). So \(Y = BC + ABC’\). This is not \(A’BC + AB\). – \(Y = A + BC\): This expression is incorrect. If \(A=0\), \(B=1\), \(C=0\), the truth table shows \(Y=0\), but \(A+BC = 0 + 1*0 = 0\). However, if \(A=0\), \(B=1\), \(C=1\), the truth table shows \(Y=1\), and \(A+BC = 0 + 1*1 = 1\). If \(A=1\), \(B=0\), \(C=0\), the truth table shows \(Y=0\), but \(A+BC = 1 + 0*0 = 1\). This option is clearly wrong. – \(Y = AB + AC\): This expression is also incorrect. If \(A=0\), \(B=1\), \(C=1\), the truth table shows \(Y=1\), but \(AB + AC = 0*1 + 0*1 = 0\). This option is incorrect. The minimal SOP form \(Y = BA + BC\) is the most efficient representation in terms of the number of literals and gates required for implementation using standard AND-OR logic, which is a fundamental consideration in digital circuit design taught at institutions like Chittagong University of Engineering & Technology. Understanding Boolean simplification is crucial for designing cost-effective and high-performance digital systems.

The question probes the understanding of fundamental principles in digital logic design, specifically related to combinational circuits and their minimization. The scenario describes a digital system designed to control a water level indicator for a reservoir at Chittagong University of Engineering & Technology (CUET). The system uses three input signals: High Water Level (H), Medium Water Level (M), and Low Water Level (L), and produces an output signal, Pump Control (P). The truth table provided dictates the pump’s behavior: the pump should be ON (P=1) when the water level is Low (L=1) and Medium (M=0), or when the water level is High (H=1) regardless of other levels. Let’s construct the truth table based on the description: | H | M | L | P | |—|—|—|—| | 0 | 0 | 0 | 0 | (No level, pump off) | 0 | 0 | 1 | 1 | (Low level, pump on) | 0 | 1 | 0 | 0 | (Medium level, pump off) | 0 | 1 | 1 | 1 | (Medium and Low level, pump on – implicitly covered by H=1 or L=1 conditions) | 1 | 0 | 0 | 1 | (High level, pump on) | 1 | 0 | 1 | 1 | (High and Low level, pump on) | 1 | 1 | 0 | 1 | (High and Medium level, pump on) | 1 | 1 | 1 | 1 | (All levels, pump on) The conditions for P=1 are: 1. L is 1 AND M is 0 ( \( \bar{M}L \) ) 2. H is 1 ( \( H \) ) Therefore, the Boolean expression for P is \( P = H + \bar{M}L \). Now, let’s analyze the given options to see which one represents this logic. The question asks for the most efficient implementation, which usually implies a minimized Boolean expression. Option a) \( P = H + \bar{M}L \) directly matches our derived expression. Let’s consider why other options might be incorrect or less efficient: Option b) \( P = H + ML \) would turn the pump ON when the water level is High OR when both Medium and Low levels are simultaneously active. This is incorrect because the pump should be ON when the level is Low (L=1) and Medium is NOT active (\( \bar{M} \)). Option c) \( P = \bar{H} + \bar{M} + \bar{L} \) represents the condition where the pump is ON if the water level is NOT High, OR NOT Medium, OR NOT Low. This is the inverse of the pump being OFF when all levels are low, and it doesn’t accurately reflect the specific conditions for pump activation. Option d) \( P = H \cdot (\bar{M} + L) \) expands to \( P = H\bar{M} + HL \). This expression is true if the water level is High and Medium is not active, or if the water level is High and Low is active. While \( HL \) is covered by \( H \) in our correct expression, \( H\bar{M} \) is not the same as \( H \) alone. The condition \( H \) alone is sufficient to turn the pump on, irrespective of \( M \) or \( L \). The expression \( H + \bar{M}L \) correctly captures that if \( H \) is 1, \( P \) is 1, regardless of \( M \) and \( L \). If \( H \) is 0, then \( P \) is 1 only if \( \bar{M} \) is 1 and \( L \) is 1. The expression \( H \cdot (\bar{M} + L) \) does not cover the case where \( H=0 \) and \( \bar{M}L=1 \) (i.e., \( H=0, M=0, L=1 \)), which should result in \( P=1 \). The expression \( P = H + \bar{M}L \) is the most direct and minimal representation of the given logic for the water level control system at CUET. This adheres to principles of efficient digital circuit design, minimizing the number of logic gates required for implementation, which is a key consideration in engineering projects at institutions like CUET. Understanding Boolean algebra and minimization techniques is fundamental for students pursuing degrees in electrical and electronic engineering or computer science and engineering at CUET, as it directly impacts the cost, speed, and power consumption of digital systems.

The question probes the understanding of fundamental principles in materials science and engineering, specifically concerning the behavior of crystalline structures under stress, a core area of study at Chittagong University of Engineering & Technology. The scenario describes a metal alloy exhibiting anisotropic elastic properties, meaning its stiffness varies with direction. This is a common characteristic of many engineering materials, particularly those with non-cubic crystal structures or those that have undergone specific processing like rolling or drawing. The core concept being tested is the relationship between stress, strain, and material properties in anisotropic materials. In such materials, Hooke’s Law, which relates stress and strain linearly, takes a more complex tensorial form. For a general anisotropic material, the relationship is expressed as: \[ \sigma_{ij} = C_{ijkl} \epsilon_{kl} \] where \( \sigma_{ij} \) is the stress tensor, \( \epsilon_{kl} \) is the strain tensor, and \( C_{ijkl} \) is the fourth-order stiffness tensor. This tensor contains many independent elastic constants, unlike isotropic materials which are characterized by only two (e.g., Young’s modulus and Poisson’s ratio). The question asks about the most appropriate method to characterize the elastic behavior of such an alloy for applications at Chittagong University of Engineering & Technology, where precision in structural design is paramount. Option (a) suggests using a single Young’s modulus and Poisson’s ratio. This is only valid for isotropic materials and would lead to inaccurate predictions for an anisotropic alloy, potentially compromising structural integrity in critical applications like bridge design or advanced manufacturing processes, both areas of focus at CUET. Option (b) proposes employing a comprehensive set of elastic constants derived from extensive mechanical testing across multiple crystallographic orientations. This approach directly addresses the anisotropic nature of the material. Techniques like tensile testing along different crystallographic axes, shear tests, and ultrasonic measurements are used to determine the full stiffness tensor. This detailed characterization is essential for accurate finite element analysis (FEA) and predictive modeling of component behavior under various loading conditions, aligning with CUET’s emphasis on rigorous engineering analysis. Option (c) advocates for averaging the elastic properties. While averaging might provide a rough estimate, it sacrifices the directional information crucial for understanding the material’s true mechanical response and can lead to significant errors in predicting performance, especially in components subjected to complex stress states. Option (d) suggests relying solely on empirical data from a limited number of specific applications. This approach is insufficient for a fundamental understanding of the material’s elastic properties and lacks the predictive power needed for designing new components or optimizing existing ones, which is a cornerstone of engineering education at CUET. Therefore, the most scientifically sound and practically relevant approach for characterizing the elastic behavior of an anisotropic metal alloy, especially in the context of advanced engineering studies at Chittagong University of Engineering & Technology, is to determine and utilize the complete set of independent elastic constants through rigorous experimental methods.

The question probes the understanding of fundamental principles in digital logic design, specifically concerning the minimization of Boolean expressions and the implications of different logic gate implementations. The core concept is Karnaugh maps (K-maps) and their application in simplifying complex logic functions to achieve efficient circuit designs, a crucial aspect in electrical and computer engineering programs at Chittagong University of Engineering & Technology. Consider a Boolean function \(F(A, B, C, D) = \Sigma m(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)\). This represents a function where all possible minterms for four variables are included. In Boolean algebra, a function that is true for all possible input combinations is equivalent to a constant ‘1’. To minimize this function using a Karnaugh map, we would fill all 16 cells of a 4-variable K-map with ‘1’s. The grouping of adjacent ‘1’s in a K-map aims to cover all ‘1’s with the minimum number of largest possible groups. When all cells are ‘1’, the entire map is covered by a single, all-encompassing group. This single group represents the simplified Boolean expression. For a 4-variable K-map, the groups correspond to terms that are independent of certain variables. For instance, a group covering a block of four cells eliminates two variables, and a group covering eight cells eliminates three variables. A group covering all sixteen cells eliminates all four variables, resulting in a constant value. In this specific case, since all minterms are present, the function \(F(A, B, C, D)\) is always true, regardless of the input values of A, B, C, and D. Therefore, the simplified Boolean expression is simply ‘1’. This signifies that the output is always high, irrespective of the inputs. This fundamental understanding of Boolean algebra and minimization techniques is vital for designing efficient digital circuits, a core competency expected of students in the Electrical and Electronic Engineering department at Chittagong University of Engineering & Technology. The ability to simplify logic functions directly impacts the number of gates required, power consumption, and propagation delay in digital systems.

The question probes the understanding of fundamental principles of electrical circuits, specifically concerning the behavior of capacitors in response to changes in voltage. In a DC circuit, once a capacitor is fully charged, it acts as an open circuit, meaning no current flows through it. This is because the dielectric material between the plates prevents the flow of charge carriers. Therefore, if a capacitor is connected in series with a resistor and a DC voltage source, and the circuit has been in operation for a sufficiently long time (steady state), the capacitor will be fully charged. At this point, the voltage across the capacitor will be equal to the source voltage, and the current flowing through the resistor (and thus the circuit) will be zero. This concept is crucial for understanding transient behavior in RC circuits and is a foundational element in many electrical engineering disciplines taught at Chittagong University of Engineering & Technology. The ability to predict the steady-state behavior of capacitive circuits is essential for designing filters, timing circuits, and power supply smoothing networks, all of which are relevant to the curriculum at CUET.

The question probes the understanding of fundamental principles of electrical circuits, specifically focusing on the behavior of components in series and parallel configurations when subjected to a varying input. The scenario describes a circuit with a resistor (\(R_1\)) and a capacitor (\(C_1\)) in series, connected to an AC voltage source. The key concept here is impedance, which is the total opposition to current flow in an AC circuit, encompassing both resistance and reactance. For a series RC circuit, the total impedance (\(Z\)) is given by \(Z = \sqrt{R^2 + X_C^2}\), where \(R\) is the resistance and \(X_C\) is the capacitive reactance. Capacitive reactance is inversely proportional to the frequency (\(f\)) of the AC source and the capacitance (\(C\)), expressed as \(X_C = \frac{1}{2\pi fC}\). In this problem, we are given that the circuit is initially operating at a frequency \(f_1\) and then the frequency is increased to \(f_2\), where \(f_2 > f_1\). As the frequency increases, the capacitive reactance (\(X_C\)) decreases because \(X_C\) is inversely proportional to \(f\). The total impedance of the series RC circuit is \(Z = \sqrt{R_1^2 + X_{C1}^2}\) at frequency \(f_1\) and \(Z = \sqrt{R_1^2 + X_{C2}^2}\) at frequency \(f_2\). Since \(f_2 > f_1\), it follows that \(X_{C2} < X_{C1}\). Consequently, \(R_1^2 + X_{C2}^2 < R_1^2 + X_{C1}^2\), which means \(Z_2 < Z_1\). According to Ohm's Law for AC circuits, the current (\(I\)) is given by \(I = \frac{V}{Z}\), where \(V\) is the RMS voltage of the source. Since the voltage source remains constant and the total impedance (\(Z\)) decreases as the frequency increases, the current (\(I\)) flowing through the circuit will increase. This principle is fundamental to understanding AC circuit analysis and is a core concept taught in electrical engineering programs at institutions like Chittagong University of Engineering & Technology. The ability to predict how circuit parameters change with frequency is crucial for designing filters, oscillators, and other signal processing systems.

The question probes the understanding of fundamental principles in materials science and engineering, particularly concerning the behavior of crystalline solids under stress, a core area for students entering programs at Chittagong University of Engineering & Technology. The scenario describes a metal alloy exhibiting a specific stress-strain relationship. The key to answering lies in recognizing that the elastic modulus (Young’s Modulus) is defined as the ratio of stress to strain in the elastic region of deformation. In the provided stress-strain curve, the elastic region is characterized by a linear relationship between stress and strain. To determine the elastic modulus, we select a point within this linear region. Let’s choose a stress value of \(150 \, \text{MPa}\). From the graph (implied by the question’s premise, though not visually provided, the question is designed to test conceptual understanding of how to derive it from such a graph), the corresponding strain at this stress is \(0.002\). Therefore, the elastic modulus \(E\) is calculated as: \(E = \frac{\text{Stress}}{\text{Strain}}\) \(E = \frac{150 \, \text{MPa}}{0.002}\) \(E = 75000 \, \text{MPa}\) \(E = 75 \, \text{GPa}\) This calculation demonstrates the direct application of the definition of elastic modulus. Understanding this concept is crucial for predicting material behavior in structural applications, a significant focus in mechanical and civil engineering disciplines at CUET. The elastic modulus dictates a material’s stiffness and its ability to return to its original shape after deformation. A higher elastic modulus signifies a stiffer material. In the context of CUET’s curriculum, this knowledge is foundational for courses in solid mechanics, materials science, and structural analysis, enabling students to design components that can withstand applied loads without permanent deformation. The ability to interpret stress-strain curves and extract critical material properties like elastic modulus is a fundamental skill for any aspiring engineer.